“Non-intrusive Runtime Verification within a System-on-Chip”
Revision as of 12:26, 1 May 2019 by Casim
Ada User Journal, pp. 296–299, Jun. 2018.
Abstract: This paper describes how to enrich a System-on-Chip (SoC) design by flexible monitoring capabilities allowing to analyze the system's execution for ensuring safety requirements. To this end, a general SoC architecture is described enriched by observation means. Moreover, it is described how verification properties expressed in a temporal stream-based specification language can be translated into a monitor expressed in a hardware description language (Verilog) checking the underlying property. Finally, the link between the SoC and the monitoring unit is explained. Overall, a self-observing system is obtained that works coherently with the SoC.
Research line(s): Timeliness and Adaptation in Dependable Systems (TADS)
Also as Proceedings of the RUME 2018 - Runtime Verification and Monitoring Technologies for Embedded Systems Workshop.