“Non-intrusive Runtime Verification within a System-on-Chip”
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|Project=Project:NORTH, Project:COST Action IC1402, | |Project=Project:NORTH, Project:COST Action IC1402, | ||
|ResearchLine=Timeliness and Adaptation in Dependable Systems (TADS) | |ResearchLine=Timeliness and Adaptation in Dependable Systems (TADS) | ||
- | |month= | + | |month=dec |
|year=2018 | |year=2018 | ||
|abstract=This paper describes how to enrich a System-on-Chip (SoC) design by flexible monitoring capabilities allowing to analyze the system's execution for ensuring safety requirements. To this end, a general SoC architecture is described enriched by observation means. Moreover, it is described how verification properties expressed in a temporal stream-based specification language can be translated into a monitor expressed in a hardware description language (Verilog) checking the underlying property. Finally, the link between the SoC and the monitoring unit is explained. Overall, a self-observing system is obtained that works coherently with the SoC. | |abstract=This paper describes how to enrich a System-on-Chip (SoC) design by flexible monitoring capabilities allowing to analyze the system's execution for ensuring safety requirements. To this end, a general SoC architecture is described enriched by observation means. Moreover, it is described how verification properties expressed in a temporal stream-based specification language can be translated into a monitor expressed in a hardware description language (Verilog) checking the underlying property. Finally, the link between the SoC and the monitoring unit is explained. Overall, a self-observing system is obtained that works coherently with the SoC. | ||
|journal=Ada User Journal | |journal=Ada User Journal | ||
+ | |volume=39 | ||
+ | |number=4 | ||
|pages=296--299 | |pages=296--299 | ||
}} | }} | ||
Also as Proceedings of the RUME 2018 - Runtime Verification and Monitoring Technologies for Embedded Systems Workshop. | Also as Proceedings of the RUME 2018 - Runtime Verification and Monitoring Technologies for Embedded Systems Workshop. |
Latest revision as of 12:37, 1 May 2019
José Rufino, Felix Dino Lange, Martin Leucker, Torben Scheffel, Malte Schmitz, Daniel Thoma, António Casimiro
Ada User Journal, vol. 39, no. 4, pp. 296–299, Dec. 2018.
Abstract: This paper describes how to enrich a System-on-Chip (SoC) design by flexible monitoring capabilities allowing to analyze the system's execution for ensuring safety requirements. To this end, a general SoC architecture is described enriched by observation means. Moreover, it is described how verification properties expressed in a temporal stream-based specification language can be translated into a monitor expressed in a hardware description language (Verilog) checking the underlying property. Finally, the link between the SoC and the monitoring unit is explained. Overall, a self-observing system is obtained that works coherently with the SoC.
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Project(s): Project:NORTH, Project:COST Action IC1402
Research line(s): Timeliness and Adaptation in Dependable Systems (TADS)
Also as Proceedings of the RUME 2018 - Runtime Verification and Monitoring Technologies for Embedded Systems Workshop.