“Mechanisms for Enhanced Dependability and Timeliness in CAN”

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The final result is a set of mechanisms specified in a Hardware Description Language (HDL), which can be fitted into a small-sized Field Programmable Gate Array (FPGA), thus providing CANELy-based applications with means for: effective redundancy management, channel and media fault detection and confinement, upper layer signalling for network operation status assessment, all in a cost-effective manner.
The final result is a set of mechanisms specified in a Hardware Description Language (HDL), which can be fitted into a small-sized Field Programmable Gate Array (FPGA), thus providing CANELy-based applications with means for: effective redundancy management, channel and media fault detection and confinement, upper layer signalling for network operation status assessment, all in a cost-effective manner.
|school=Universidade Técnica de Lisboa, Instituto Superior Técnico
|school=Universidade Técnica de Lisboa, Instituto Superior Técnico
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|advisor=José Rufino,  
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|advisor=José Rufino, Carlos Almeida
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Revision as of 16:50, 31 March 2017

Ricardo Correia Pinto (advised by José Rufino, Carlos Almeida)

Master’s thesis, Universidade Técnica de Lisboa, Instituto Superior Técnico, Dec. 2010

Abstract: A cost-effective solution for Distributed Control System (DCS) interconnection is the Controller Area Network (CAN) fieldbus. Designed to be used in the harsh automotive environment, its usage has spread to other domains, e.g. home automation, elevators, shop-floor control and even aerospace applications. However, there is a set of domains where CAN could not be used without additional mechanisms: mission-critical applications. In fact, despite exhibiting fault-tolerant behaviour in the presence of errors, CAN fault coverage alone is not high enough to meet the stringent requirements regarding safety, availability and reliability these domains demand. The CAN Enhanced Layer (CANELy) architecture is a step towards a CAN-based high dependability architecture, through the provision of: reliable communication services, network reliability and availability, channel timeliness guarantees. This work discusses the design and implementation of effective mechanisms for network dependability and timeliness enhancement, in the context of the CANELy architecture. Our working basis is the extended fault model provided by the CANELy architecture, which contemplates the utilisation of media redundancy for the communication channel. From this basis we identified effective mechanisms to detect and isolate faults affecting either the channel or any of the redundant media conveying the channel. The final result is a set of mechanisms specified in a Hardware Description Language (HDL), which can be fitted into a small-sized Field Programmable Gate Array (FPGA), thus providing CANELy-based applications with means for: effective redundancy management, channel and media fault detection and confinement, upper layer signalling for network operation status assessment, all in a cost-effective manner.


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Research line(s): Timeliness and Adaptation in Dependable Systems (TADS)

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